domstat.net

Website loading time

during the test: s

cable connection (average): s

DSL connection (average): s

modem (average): s

HTTP headers

1

14.44

24

0.56

0.6

0.64

2.62

Information about DNS servers

Received from the first DNS server

Received from the second DNS server

Request to the server "opencores.org"
You used the following DNS server:
DNS Name: dns2.technorail.com
DNS Server Address: 62.149.132.2#53
DNS server aliases:

HEADER opcode: REQUEST, status: NOERROR, id: 50992
flag: qr rd ra REQUEST: 1, ANSWER: 5, AUTHORITY: 0, ADDITIONAL: 3

REQUEST SECTION:
opencores.org. IN ANY

ANSWER SECTION:
opencores.org. 600 IN A 92.43.36.68
opencores.org. 600 IN NS dns2.se.
opencores.org. 600 IN MX 0 mail.opencores.org.
opencores.org. 600 IN SOA dns1.se. marcus.erlandsson.gmail.com. 2011091501 28800 7200 604800 600
opencores.org. 600 IN NS dns1.se.

SECTION NOTES:
mail.opencores.org. 600 IN A 92.43.36.68
dns1.se. 600 IN A 195.35.82.140
dns2.se. 599 IN A 88.131.30.99

Received 219 bytes from address 62.149.132.2#53 in 336 ms

Subdomains (the first 50)

Typos (misspells)

Location

IP: 92.43.36.68

continent: EU, country: Sweden (SWE), city:

Website value

rank in the traffic statistics: the

There is not enough data to estimate website value.

Basic information

website build without CSS

code weight: utf-8 KB

text per all code ratio: en %

title: Home :: OpenCores

description:

keywords: cores, VHDL, Verilog HDL, ASIC, Synthesizable, standard cell, IP, Intellectual Property, 32-bit RISC, UART, PCI, SDRAM, full custom, system on a chip, SOC, reusable, design, development, synthesis, designs, developers, C, Linux, eCos, open, free, open source cores, RTL code, system-on-a-chip, circuits, digital, GNU, GPL, core, controller, processor, system design, chip design, EDA, design methodology, design tools, ASICs, programmable logic, FPGA's, PLDs, CPLDs, verification, Synthesis, HDL, Simulation, IC design software, semiconductor design, integrated circuits, system designs, chip designs, EDAs, design methodologies, design tool, ASIC, programmable logics, FPGA, PLD, CPLD, Synthesis, circuit, Synopsys, system design, chip design, programmable logic, FPGA's, PLDs, CPLDs, verification, Simulation

encoding:

language:

Website code analysis

one word phrases repeated minimum three times

two word phrases repeated minimum three times

three word phrases repeated minimum three times

B tags

U tags

I tags

images

headers

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internal links

external links